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19-2210; Rev 1; 10/02
Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs
General Description
The MAX6391/MAX6392 microprocessor (P) supervisory circuits provide sequenced logic reset outputs for multicomponent or dual-voltage systems. Each device can monitor two supply voltages and time-sequence two reset outputs to control the order in which system components are turned on and off. The MAX6391/MAX6392 increase system reliability and reduce circuit complexity and cost compared to separate ICs or discrete components. The MAX6391/MAX6392 monitor V CC as the master reset supply. Both RESET1 and RESET2 are asserted whenever VCC drops below the selected factory-fixed reset threshold voltage. RESET1 remains asserted as long as V CC is below the threshold and deasserts 140ms (min) after VCC exceeds the thresholds. RESET IN2 is monitored as the secondary reset supply and is adjustable with an external resistive-divider network. RESET2 is asserted whenever either V CC or RESET IN2 is below the selected thresholds. RESET2 remains asserted 140ms (min) or a capacitoradjustable time period after V CC and RESET IN2 exceed their thresholds. RESET2 is always deasserted after RESET1 during system power-up and is always asserted before RESET1 during power-down. The MAX6391 includes two internal pullup resistors for RESET1 and RESET2 (the open-drain outputs can be externally connected to the desired pullup voltages). The MAX6392 includes an active-low manual reset input (MR) that asserts both RESET1 (push-pull) and RESET2 (open drain). The MAX6391/MAX6392 are available in small 8-pin SOT23 packages and are specified over the -40C to +85C extended temperature range.
Features
o Preset VCC Reset Threshold Voltages from 1.58V to 4.63V (master supply) o Customer-Adjustable RESET IN2 to Monitor Voltages Down to 625mV (secondary supply) o Fixed (140ms min) RESET1 Timeout o Fixed (140ms min) or Customer-Adjustable RESET2 Timeout Period o Guaranteed Reset Valid to VCC = 1V o Active-Low Open-Drain Outputs or PushPull/Open-Drain Combination o Internal Open-Drain Pullup Resistors (for external VOH voltage connections) o Manual Reset Input (MAX6392 only) o Immune to Short Negative VCC Transients o 15A Typical Supply Current o Few External Components o Small 8-Pin SOT23 Package
MAX6391/MAX6392
Ordering Information
PART* MAX6391KA_ _-T MAX6392KA_ _-T TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE SOT23-8 SOT23-8
Applications
Computers Controllers Critical P Power Monitoring Set-Top Boxes Printers Servers/Workstations Industrial Equipment Multivoltage Monitoring
*Insert the desired suffix (see Selector Guide) into the blanks to complete the part number. The MAX6391/MAX6392 require a 2.5k minimum order increment and are available in tape-andreel only. Samples are typically available for standard versions (see Selector Guide for standard versions). Contact factory for availability.
Pin Configurations
TOP VIEW
RESET IN2 1 VCC 2 CSRT 3 8 7 R1 RESET1 R2 RESET2
MAX6391
6 5
GND 4
SOT23-8 Typical Operating Circuit appears at end of data sheet. Pin Configurations continued at end of data sheet. 1
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Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs MAX6391/MAX6392
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +6.0V RESET1 (MAX6392), RESET IN2, CSRT, MR to GND ..............................................-0.3V to (VCC + 0.3V) RESET1 (MAX6391), RESET2, R1, R2 to GND......-0.3V to +6.0V Input Current (VCC, GND, CSRT, R1, R2, MR) .................20mA Output Current (RESET1, RESET2) ..................................20mA Continuous Power Dissipation (TA = +70C) 8-Pin SOT23 (derate 5.26mW/C above +70C)...........421mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25C.) (Note 1)
PARAMETER VCC Range Supply Current ICC SYMBOL CONDITIONS TA = 0C to +85C TA = -40C to +85C No load MAX639_UA46 MAX639_UA44 MAX639_UA31 MAX639_UA29 VCC Reset Threshold VTH1 MAX639_UA26 MAX639_UA23 MAX639_UA22 MAX639_UA17 MAX639_UA16 RESET IN2 Threshold RESET IN2 Input Current VCC to RESET1 Delay VCC or RESET IN2 to RESET2 Delay tRD1 tRD2 VCC falling at 1mV/s (Note 2) 20 10 s VTH2 VCC = 5V 4.50 4.25 3.00 2.85 2.55 2.25 2.12 1.62 1.54 610 MIN 1.0 1.2 15 4.63 4.38 3.08 2.93 2.63 2.32 2.19 1.67 1.58 625 TYP MAX 5.5 5.5 25 4.75 4.50 3.15 3.00 2.70 2.38 2.25 1.71 1.61 640 50 mV nA V UNITS V A
2
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Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = +5V and TA = +25C.) (Note 1)
PARAMETER RESET1 Timeout Period RESET2 Timeout Period (Note 3) SYMBOL tRP1 tRP2 CCSRT = 1500pF CCSRT = VCC ISINK = 50A, reset asserted VOL VCC 1.0V, TA = 0C to +85C VCC 1.2V, TA = -40C to +85C CONDITIONS MIN 140 2.2 140 TYP 200 3.1 200 MAX 280 4.0 280 0.3 0.3 0.3 0.4 1.0 A V UNITS ms ms
MAX6391/MAX6392
RESET_ Output Voltage Low
ISINK = 1.2mA, reset asserted, VCC 2.5V ISINK = 3.2mA, reset asserted, VCC 4.25V Open-Drain RESET Output Leakage Current Push-Pull RESET1 Output Voltage High (MAX6392 only) ILKG VCC VTH1, VRESET IN2 VTH2, reset not asserted VCC 2.25V, ISOURCE = 500A, reset not asserted VOH VCC 4.5V, ISOURCE = 800A, reset not asserted VCC > 4.0V 2.4
0.8 VCC 0.8 0.3 VCC 0.7 VCC 50 100
V
VIL VIH MR Input VIL
V
VCC < 4.0V VIH MR Minimum Pulse Width MR Glitch Rejection MR to RESET1 Delay MR to RESET2 Delay tMR Skew MR Pullup Resistance Reset Pullup Resistance tMR1 tMR2 tMR1 - tMR2 Pullup to VCC RESET1 to R1 or RESET2 to R2
s ns s ns s 60 60 k k 10 100 10
35 35
47 47
Note 1: Overtemperature limits are guaranteed by design and not production tested. Devices tested at +25C only. Note 2: RESET2 asserts before RESET1 when VCC goes below the threshold for all supply voltage and temperature ranges. Note 3: CSRT must be connected to either VCC (for fixed RESET2 timeout period) or an external capacitor (for useradjustable RESET2 timeout period).
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3
Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs MAX6391/MAX6392
Typical Operating Characteristics
(VCC = +5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX6391 toc01
VCC FALLING TO RESET1 DELAY VS. TEMPERATURE
MAX6391 toc02
VCC FALLING TO RESET2 DELAY vs. TEMPERATURE
16 15 DELAY (s) 14 13 12 11 10 9
MAX6391 toc03
17
28 27 26 DELAY (s) 25 24 23
17
SUPPLY CURRENT (A)
16
15
14
22 21
13 -40 -15 10 35 60 85 TEMPERATURE (C)
20 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
TEMPERATURE (C)
RESET2 TO RESET1 DELAY vs. TEMPERATURE
MAX6391 toc04
RESET1 TIMEOUT PERIOD vs. TEMPERATURE
MAX6391 toc05
RESET1 TO RESET2 TIMEOUT PERIOD vs. TEMPERATURE (CSRT = 1500pF)
MAX6391 toc06
11.8
300
3.50
11.6 DELAY (s)
TIMEOUT DELAY (ms)
11.4
250
TIMEOUT DELAY (ms) -40 -15 10 35 60 85
275
3.25
3.00
11.2
11.0
225
2.75
10.8 -40 -15 10 35 60 85 TEMPERATURE (C)
200 TEMPERATURE (C)
2.50 -40 -15 10 35 60 85 TEMPERATURE (C)
RESET1 TO RESET2 TIMEOUT PERIOD vs. TEMPERATURE (CSRT TIED TO VCC)
MAX6391 toc07
MAXIMUM TRANSIENT DURATION vs. RESET COMPARATOR OVERDRIVE
MAXIMUM TRANSIENT DURATION (s)
MAX6391 toc08
300
60
50
TIMEOUT DELAY (ms)
275
40 RESET ASSERTS ABOVE THIS LINE 30
250
225
20
200 -40 -15 10 35 60 85 TEMPERATURE (C)
10 1 10 100 1000 OVERDRIVE (mV)
4
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Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs
Pin Description
PIN MAX6391 1 2 3 4 MAX6392 1 2 3 4 NAME FUNCTION Input Voltage for RESET2 Monitor. High-impedance input for internal reset comparator. Connect this pin to an external resistive-divider network to set the reset threshold voltage. Supply Voltage and Input Voltage for Primary Supply Monitor RESET2 Delay Set Capacitor. Connect to VCC for a fixed 140ms (min) timeout period or to an external capacitor for a user-adjustable timeout period after VCC exceeds its minimum threshold. Ground Secondary Reset Output, Open-Drain, Active-Low. RESET2 changes from high to low when either VCC or RESET IN2 drop below their thresholds. RESET2 remains low for a user-adjustable timeout period (see CSRT) or a fixed 140ms (min) after VCC and RESET IN2 meet their minimum thresholds. 47k Internal Pullup Resistor for RESET2. Connect to external voltage for RESET2 high pullup. Primary Reset Output, Open-Drain (MAX6391) or Push-Pull (MAX6392), Active-Low. RESET1 changes from HIGH to LOW when the VCC input drops below the selected reset threshold. RESET1 remains LOW for the reset timeout period after VCC exceeds the minimum threshold. 47k Internal Pullup Resistor for RESET1. Connect to external voltage for RESET1 high pullup. Manual Reset, Active-Low, Internal 47k Pullup to VCC. Pull LOW to force a reset. RESET1 and RESET2 remain asserted as long as MR is LOW and for the RESET1 and RESET2 timeout periods after MR goes HIGH. Leave unconnected or connect to VCC if unused.
MAX6391/MAX6392
RESET IN2 VCC CSRT GND
5
5
RESET2
6
6
R2
7
7
RESET1
8
--
R1
--
8
MR
Detailed Description
Each device includes a pair of voltage monitors with sequenced reset outputs. The first block monitors VCC only (RESET1 output is independent of the RESET IN2 monitor). It asserts a reset signal (LOW) whenever VCC is below the preset voltage threshold. RESET1 remains asserted for at least 140ms after VCC rises above the reset threshold. RESET1 timing is internally set in each device. V CC voltage thresholds are available from 1.57V to 4.63V. In all cases VCC acts as the master supply (all resets are asserted when VCC goes below its selected threshold). The VCC input also acts as the device power supply. The second block monitors both RESET IN2 and VCC. It asserts a reset signal (LOW) whenever RESET IN2 is below the 625mV threshold or VCC is below its reset threshold. RESET2 remains asserted for a fixed 140ms
(min) or a user-adjustable time period after RESET IN2 rises above the 625mV reset threshold and RESET1 is deasserted. Resets are guaranteed valid for VCC down to 1V. The timing diagram in Figure 2 shows the reset timing characteristics of the MAX6391/MAX6392. As shown in Figure 2, RESET1 deasserts 140ms (min) (tRP1) after VCC exceeds the reset threshold. RESET2 deasserts tRP2 (140ms minimum or a user-adjustable timeout period) after RESET IN2 exceeds 625mV and RESET1 is deasserted. When RESET IN2 drops below 625mV while VCC is above the reset threshold, RESET2 asserts within 10s typ. RESET1 is unaffected when this happens. When V CC falls below V TH1 , RESET2 always asserts before RESET1 (tRD2 < tRD1).
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5
Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs MAX6391/MAX6392
MR (MAX6392 ONLY)
VCC MR PULLUP MR DETECT VCC (MAX6392 ONLY) 47k FIXED RESET TIMEOUT PERIOD 1.25V VCC R2 47k FIXED OR CAPACITORADJUSTABLE RESET TIMEOUT PERIOD RESET IN2 RESET2 RESET1 R1 (MAX6391 ONLY)
0.625V
CSRT
Figure 1. Functional Diagram
VTH1 VCC tRP1
VTH1
tRD1
RESET1
VTH2 RESET IN2 tRP2 tRD2
VTH2
tRP2
tRD2
RESET2
Figure 2. Timing Diagram 6 _______________________________________________________________________________________
Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs
Selector Guide
PART NUMBER MAX6391KA46 MAX6391KA44 MAX6391KA31 MAX6391KA29 MAX6391KA26 MAX6391KA23 MAX6391KA22 MAX6391KA17 MAX6391KA16 MAX6392KA46 MAX6392KA44 MAX6392KA31 MAX6392KA29 MAX6392KA26 MAX6392KA23 MAX6392KA22 MAX6392KA17 MAX6392KA16 NOMINAL THRESHOLD (V) 4.63 4.38 3.08 2.93 2.63 2.32 2.19 1.67 1.58 4.63 4.38 3.08 2.93 2.63 2.32 2.19 1.67 1.58 TOP MARK AAHJ AAHK AAHL AAHM AAHN AAHO AAHP AAHQ AAHR AAHS AAHT AAHU AAHV AAHW AAHX AAHY AAHZ AAIA
chain. The MAX6391 internally determines the CSRT connection and provides the proper timing setup. In all cases, RESET IN2 acts as the slave supply. VCC can assert the RESET2 output but RESET IN2 will have no effect on the RESET1 output.
MAX6391/MAX6392
Monitoring Voltages Other Than VCC
An external resistive-divider network is required at RESET IN2 for most applications. The divider resistors, R3 and R4, may be calculated by the following formula: VRST = VTH2 (R3 + R4)/R4 where VTH2 = 625mV (internal reference voltage) and VRST is the desired reset threshold voltage. R4 may be set to a conveniently high value (500k for example, to minimize current consumption) and the equation may be solved for R3 by: R3 = R4 (VRST/VTH2 - 1) For single-supply operations requiring two reset outputs (RESET1 before RESET2), connect RESET IN2 directly to VCC and adjust RESET2 timeout delay with CCRST as desired.
Pullup Resistors
The MAX6391 includes open-drain outputs for both RESET1 and RESET2. Two internal resistors, R1 and R2, of 47k each are provided with internal connections to RESET1 and RESET2. These resistors may be connected to the appropriate external voltage for independent V OH drive with no additional component requirements. The MAX6392 includes a manual reset option, MR, that replaces the R1 pullup resistor. The active-low manual reset input forces both RESET1 and RESET2 low. RESET2 is driven active before RESET1 in all cases (10s typ). The resets follow standard reset timing specifications after the manual reset is released. The manual reset is internally pulled up to VCC through a 47k resistor.
Standard versions in bold face. Samples are typically available for standard versions. Contact factory for availability.
Applications Information
Selecting the Reset Timeout Capacitor
The RESET2 delay may be adjusted by the user with an external capacitor connected from the CSRT pin to ground. The MAX6391 includes a 600nA current source that is switched to CCSRT to create a voltage ramp. The voltage ramp is compared to the internal 1.25V reference to set the RESET2 delay period. The period is calculated by: t = C V/I where V = 1.25V, I = 600nA, and C is the external capacitor. Simplifying, tRP = 2.08 106 s / F CCSRT For CCSRT = 1500pF, tRP = 3.1ms A fixed internal 140ms (min) reset delay time for RESET2 may be chosen by connecting the CSRT pin to VCC. The VCC to CSRT connection disables the voltage ramp and enables a separate fixed delay counter
Negative-Going VCC Transients
In addition to issuing a reset to the P during power-up, power-down, and brownout conditions, these devices are relatively immune to short-duration, negative-going VCC or RESET IN2 transients (glitches). The Typical Operating Characteristics show the Maximum Transient Duration vs. Reset Comparator Overdrive graph. The graph shows the maximum pulse width that a negativegoing VCC transient may typically have without issuing a reset signal. As the amplitude of the transient increases, the maximum allowable pulse width decreases.
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7
Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs MAX6391/MAX6392
Typical Operating Circuit
VCC = 3.3V MASTER PROCESSOR RESET
VCC
RESET1
MAX6392 GND R2 R3 MR RSTIN2 R4 CSRT RESET2 SLAVE PROCESSOR RESET VCC = 1.8V
CCSRT
Pin Configurations (continued)
TOP VIEW
Chip Information
TRANSISTOR COUNT: 810 PROCESS: BiCMOS
RESET IN2 1 VCC 2 CSRT 3
8 7
MR RESET1 R2 RESET2
MAX6392
6 5
GND 4
SOT23-8
8
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Dual-Voltage P Supervisory Circuits with Sequenced Reset Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
SOT23, 8L.EPS
MAX6391/MAX6392
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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